Due to their favorable electron transport properties, the use of III-V materials (i.e., materials that include at least one group III element and at least one group V element) has been proposed for future generations of complementary metal oxide semiconductor (CMOS) circuits. However, there are a few challenges associated with the use of III-V materials in field effect transistors (FETs). For example, a p-channel FET with a III-V material does not have good interface quality and does not have good hole mobility. These drawbacks have thus far been a barrier for widespread application of III-V materials in CMOS circuits.
Therefore, techniques that permit the integration of III-V materials in CMOS circuits without the above-described drawbacks would be desirable.